Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Stages∗

Energy efficiency is a primary concern for microprocessor designers. One very effective approach to improving the energy efficiency is to lower chip supply voltage very near to the transistor threshold voltage. This reduces power consumption dramatically, improving energy efficiency by an order of magnitude. Low voltage operation, however, increases the effects of parameter variation resulting in significant frequency heterogeneity between (and within) otherwise identical cores. This heterogeneity severely limits the maximum frequency of the entire CMP. We present a combination of techniques aimed at reducing the effects of variation on the performance and energy efficiency of near-threshold, manycore CMPs. Dual Voltage Rail (DVR), mitigates core-to-core variation with a dual-rail power delivery system that allows post-manufacturing assignment of different supply voltages to individual cores. This speeds up slow cores by assigning them to a higher voltage and saves power on fast cores by assigning them to a lower voltage. Half-Speed Unit (HSU) mitigates within-core variation by halving the frequency of select functional blocks with the goal of boosting the frequency of individual cores, thus raising the frequency ceiling for the entire CMP. Together, these variation-reduction techniques result in almost 50% improvement in CMP performance for the same power consumption over a mix of workloads.